module register (clock,di,do,load);

input  [15:0] di ;
output [15:0] do ;
input         clock, load;

reg [15:0] do, di_buffer; 

`include ".\\timing.v"

initial
  begin
  do=0; di_buffer=0;
  end

always @ (posedge clock)

  if(load) begin 
    di_buffer=di;
    // $display("%t %m, di = %h", $time, di);
    #TREG do=di_buffer;
    $display("%t %m, do = %h", $time, do);
  end

endmodule