module registersatzb (a_in, sel_a, sel_b, a_out, b_out, load, clock);

input  [15:0] a_in ;
input  [2:0] sel_a, sel_b ;
output [15:0] a_out, b_out ;

input  clock, load;
reg    [15:0] data[7:0], a_out, b_out,i;

always @(sel_a or sel_b)
$display("%t %m sel_A: %dd, sel_B: %dd", $time, sel_a, sel_b);

always @(sel_a or sel_b)
begin
    a_out = data[sel_a]; b_out = data[sel_b];
    $display("%t %m A_out: %hh, B_out: %hh", $time, a_out, b_out);
end

always @(posedge clock)
begin
   a_out = data[sel_a]; b_out = data[sel_b];
   $display("%t %m A_out: %hh, B_out: %hh", $time, a_out, b_out);
   if (load == 1)
   begin
      data[sel_a] = a_in;
      $display("%t %m %hh was written to register %d.", $time, a_in, sel_a);
      for (i=0; i<8; i = i +1)
        $display("%t %m Register %d: %hh", $time, i, data[i]);
   end
end

endmodule