module sram(CS,WR,ABUS,DATABUS,SFLAG);

input CS;                       // active hi chip select
input WR;                       // active hi write control
input [15:0] ABUS;              // 16-bit address bus
inout [15:0] DATABUS;           // 16-bit data bus
input SFLAG;                    // save memory to file

reg  [15:0] DATABUS_driver;
wire [15:0] DATABUS = DATABUS_driver;
reg [15:0] ram[0:255];                   // memory cells (nur die unteren 256 !!)
integer i,fhandle,iread,iwrite;


initial                                 //initialize all RAM cells to 0 at startup
   begin
   DATABUS_driver = 16'bzzzzzzzzzzzzzzzz;
   for (i=0; i <= 10; i = i + 1)
     ram[i] = 0;
   $readmemh (".\\init.dat", ram) ;
   iread=0;
   iwrite=0;
   end

`include ".\\timing.v"

always @(CS or WR or ABUS)  //or ABUS
  begin
  #TDRIVE  if (CS == 1'b1)   // wait TDRIVE ns, then test if selected
      begin
      if (WR == 1'b1) //start writing to sram, data will be latched in on falling edge of CS or WR
        begin
        DATABUS_driver <= #TDRIVE 16'bzzzzzzzzzzzzzzzz;
        @(negedge CS or negedge WR);
        $display("%t: Writing %m ABUS=%h DATA=%h",$time,ABUS,DATABUS);
        ram[ABUS] = DATABUS;
        end
	if (CS == 1'b1)   // still selected (handle write->read sequence)
	  begin
          if (WR == 1'b0) //reading from sram (data becomes valid after TDRIVE+TMEMACC+TDRIVE ns)
           	begin
        	#TDRIVE DATABUS_driver = 16'bxxxxxxxxxxxxxxxx;
        	#TMEMACC if ((WR == 1'b0)&(CS == 1'b1))
        	     begin
        	     #TDRIVE DATABUS_driver =  ram[ABUS];
        	     $display("%t: Reading %m ABUS=%h DATA=%h",$time,ABUS,DATABUS_driver);
        	     end
               else
        	     $display("%t: timingerror CS or WR during read",$time); 
		end
        end		// still selected
	  else //sram unselected, stop driving bus after TDRIVE ns
      	begin
      	DATABUS_driver <=  #TDRIVE 16'bzzzzzzzzzzzzzzzz;
      	end
 	end  // selected
    else //sram unselected, stop driving bus after 10ns
      begin
      DATABUS_driver <=  #TDRIVE 16'bzzzzzzzzzzzzzzzz;
      end
  end

always @(posedge SFLAG)
  begin
    fhandle=$fopen(".\\savemem.dat");
    if(fhandle)
    begin
      for(i=0;i<=255;i=i+1)
         $fwrite(fhandle,"%H\n",ram[i]);
      $fclose(fhandle);
    end
  end


specify
$width (posedge WR, 70);
endspecify

specify
$width (posedge CS, 80);
endspecify

endmodule